+ :i< Rt^RIHt^RIHtHtHt^RIHt^RI H t ^RI H t ^RI HtHtHtRRltRt!R R ]4tR tR tR tRtRt!RR]4t]tRRlt]R4tR#)z Contains CUDA API functions )contextmanager)require_contextresetgpusFakeCUDAKernel) is_signaturewarn)InOutInOutc"V^8XgQR4hR#)z/Only a single device supported by the simulatorN)devs&V/var/www/html/photoedit/myenv/lib/python3.14/site-packages/numba/cuda/simulator/api.py select_devicers !8FFF8cR#)Trrrris_float16_supportedrs rc:a]tRt^toRt]R4tRtRtVt R#)streamz The stream API is supported in the simulator - however, all execution occurs synchronously, so synchronization requires no operation. c#"RxR#5iNrselfs&rauto_synchronizestream.auto_synchronizes  cR#rrrs&r synchronizestream.synchronize! rrN) __name__ __module__ __qualname____firstlineno____doc__rrr!__static_attributes____classdictcell__ __classdict__s@rrrs(  rrcR#rrrrrr!r!%rcR\nR#)TN)rclosedrrrcloser1)s DKrcR#rr)argskwargss*,rdeclare_devicer5-r.rcd\R4\RR,4\RR,4R#)zFound 1 CUDA deviceszid %d %20s %40sz %40s: 5.0zcompute capabilityN)r SIMULATORz [SUPPORTED])printrrrdetectr91s( ! !@ @A +, ,-rc\#r)rrrr list_devicesr;7s KrcDa]tRt^=toRtRRltRRltRtRtRt Vt R#) Eventz The simulator supports the event API, but they do not record timing info, and all simulation is synchronous. Execution time is not recorded. cR#rrrrs&&rrecord Event.recordBr#rcR#rrr?s&&rwait Event.waitEr#rcR#rrrs&rr!Event.synchronizeHr#rc\R4R#)zSimulator timings are bogusgr )revents&&r elapsed_timeEvent.elapsed_timeKs *+rrNr) r$r%r&r'r(r@rCr!rIr)r*r+s@rr=r==s#   rr=Nc aaaV'd \R4hVe \R4hVe(\V4'g\V\4'd VVV3Rlp V #\ VSSR7#)z)bounds checking is not supported for CUDAz Cannot link PTX in the simulatorc"<\VSSSR7#))devicefastmathdebugr)fnrPrNrOs&r jitwrapperjit..jitwrapperbs!")/+3(-/ /r)rNrP)NotImplementedErrorr isinstancelistr) func_or_sigrNrPargtypesinlinerestyperOlink boundscheckoptcacherRs &ff&&&f&&&& rjitr_Ssa !"MNN !"DEE |K88+t,, /  +fE BBrc#"RxR#5irrrrr defer_cleanupraks  rrK) NFFNFNFNNTN)r( contextlibrcudadrv.devicesrrrkernelrnumba.core.sigutilsrwarningsr r3r r r rrobjectrr!r1r5r9r;r=rHr_rarrrrhs &99",!!G  V    .  F& C0  r